The invention relates to electronic devices, and, more particularly, to channel modulation codes and methods.
Magnetic recording systems for digital data storage may have a functional structure as illustrated in FIG. 1. Briefly, for a write of data to storage, data bits typically first receive error correction encoding (such as Reed-Solomon); this coding aims to correct errors generated in the write-read process and which escape correction by the detection method of the read process. Further, interleaving blocks of error correction encoded bits helps correct bursts of errors by spreading the errors over many blocks. Next, the error correction encoded bits are modulation (channel) coded (such as runlength-limited coding); the modulation coding helps read timing recovery. A further preceding may be included. Then the modulation coded bits modulate the polarity of the write current in a read/write head over the magnetic media (e.g., a spinning disk) to set the magnetization directions of domains in the magnetic media. The pattern of magnetization directions is the stored data.
The read process begins with sensing the domain magnetization directions by voltages induced in the read/write head. After amplification the sensed voltages drive clocked analog-to-digital converters to yield a stream of digital samples. Noise in the read sensing, amplification, and conversion generates errors in the stream of digital samples. A detector (such as a peak detector or a Viterbi maximum likelihood detector) recovers the modulation encoded bits from the stream of digital samples. The modulation decoder then converts the coded bits to the error corrected bits, and lastly, the deinterleaver and error correction decoder corrects errors and recovers the data bits.
In more detail, for systems using peak detection of the digital samples, the times between sampled pulses is used to reconstruct the timing information of the stored data. In particular, the output of a peak detector controls a phase-locked loop of a controlled oscillator which provides the output clock. Absolute time cannot be used due to the variations in the speed of the magnetic media over time.
Runlength-limited encoding improves the phase-locked loop accuracy by limiting the time duration between pulses. Runlength-limited coding bounds the time duration between read signal pulse transitions, so the phase-locked loop cannot drift too far from the correct phase or frequency. That is, runlength-limited codes have constraints on the runs of 0's and 1's. A (d,k) constraint with d and k nonnegative integers means a minimum of d 0's between successive 1's and a maximum of k 0's between successive 1's. The d constraint prevents crowding of 1's and deters intersymbol interference in peak detection systems. The k constraint insures sufficiently frequent transitions to keep the phase-locked loop accurate. The k constraint also helps automatic gain control for the amplified sensed currents or voltages used with partial response detection.
In contrast to peak detection, partial response signaling allows for a controlled amount of intersymbol interference; that is, each sample has a value representing contributions from more than one pulse induced in the read/write head. Hence, a partial response system views intersymbol interference as inherent and the d constraint typically may be taken equal to 0. The k constraint still provides the phase-lock loop accuracy in partial response signaling.
Various classes of frequency response for the signal channel prior to detection have been defined; and the class IV response appears particularly suitable for magnetic recording due to pulse shapes requiring minimal equalization. The partial response class IV channel is defined by a channel transfer function polynomial of the form (1-D)(1+D).sub.N where N is a positive integer and D is a one period delay. FIGS. 2a-2c show the voltage pulse shapes induced by an isolated magnetization domain transition for N=1, 2, and 3; the corresponding pulses are termed PR4, EPR4, and E.sup.2 PR4 (or EEPR4). Thus an ideal (E)PR4 sensed voltage as a function of time consists of a sequence of overlapping (E)PR4 pulses spaced one period apart and with positive, negative, or zero amplitudes depending upon the corresponding channel bits encoded. The positive and negative amplitudes alternate corresponding to the alternation of the magnetization domain polarities. The sampling of the (E)PR4 sensed voltage yields the digital stream input to the detector, typically a sequence detector such as a maximum likelihood Viterbi decoder.
Note that the PR4 digital stream can be split into even and odd sample streams because the sampled PR4 dibit has only two nonzero values separated by one zero value (recall the 1-D response factor turns a user bit into a pair of overlapping PR4 pulses with opposite signs). In this case, the even and odd streams can be separately decoded in parallel and the runlength-limited coding thus needs a further constraint for a maximum number of 0's between successive 1's. The constraint thus takes the form of (d, G/I) where d again is the minimum number of 0's between successive 1's and G is the maximum number of 0's between successive 1's (Global constraint) plus I is the maximum number of 0's between successive 1's in each of the even and odd substreams (Interleave constraint).
Runlength-limited channel codes are block codes, and the convenience of bytewise (8 bits) treatment has led to a focus on data blocks of multiples of 8 bits. For example, a rate 8/9 (d, G/I) code maps 8-bit blocks into 9-bit blocks where the resulting bitstream of 9-bit blocks satisfies the constraint (d, G/I). The code can be described simply by listing the 256 possible 8-bit blocks and the 256 corresponding 9-bit blocks. Of course, a ROM could hold this mapping, but certain mappings may have simpler hardware implementations.
The coding efficiency of a rate 8/9 (d, G/I) code is essentially 88.9% because 8 input bits are coded by 9 output bits.
U.S. Pat. No. 5,635,933 discloses a rate 16/17 (0, 6/7) runlength-limited code which maps 16-bit input blocks into 17-bit output blocks and satisfies the constraints d=0, G=6, and I=7. Thus this code increases the coding efficiency to 94.1% and the constraint has sufficiently low G and I to permit good timing recovery. Similarly, U.S. Pat. No. 5,757,822 discloses a 16/17 (0, 7/11) code.
Rate 24/25 (d, G/l) codes further increase coding efficiency to 96%, and would be preferable provided the constraint is satisfactory. U.S. Pat. No. 5,757,294 discloses rate 24/25 (0, 14/13) and rate 24/25 (0, 11/.infin.) codes. However, G=14 is probably too high, and I=.infin. is too high.
Further, error propagation in a runlength-limited code depends upon the range of influence input bits have on output bits. In particular, Viterbi detectors in partial response channels typically output errors most often in certain patterns such as error bit, correct bit, error bit. And if the runlength-limited code converts such an error pattern into errors spanning three or four bytes, then the errors may be uncorrectable by the error correction decoder or they may diminish the correction capability of the error correction coder on further errors. Of course, as coding efficiency increases, expected error propagation would become worse due to the large block size.
Known runlength-limited coding has problems including achievement of high code efficiency with adequate constraints plus suppression of error propagation.